1. Field of the Invention
The present invention generally relates to a liquid crystal display device, and more specifically, to a wide view angle liquid crystal display device operable in an IPS (In-Plane Switching) mode.
2. Description of the Related Art
In general, there are two different modes of liquid crystal display devices (LCD). That is, in an TN (Twisted Nematic) mode LCD, a direction of a molecular axis (will be referred to as a "director" hereinafter) of oriented liquid crystal molecules is rotated along a vertical direction with respect to a substrate so as to perform an LCD display. In an IPS (In-Plane switching) mode LCD, a director of oriented liquid crystal molecules is rotated within a horizontal plane with respect to a substrate so as to execute an LCD display.
As to the IPS mode of the LCD device, even when a visual point is moved, only the short axial direction of the liquid crystal molecules is basically observed. As a result, the wide view angle can be achieved without view angle dependency of "rising ways" of the liquid crystal molecules, as compared with a TN mode of a liquid crystal display. As a consequence, such an IPS mode of a liquid crystal display device will be called a "wide view angle liquid crystal display device".
Conventionally, in this sort of wide view angle liquid crystal display device, as described in, for instance, Japanese Patent Laid-open Application No. Hei6-148595 published in 1994, the pixel electrodes and the common electrodes, which are used to apply the electric field to the liquid crystal are provided in such a manner that these electrodes are arrayed in a predetermined interval within the same plane. The electric field is applied between both the pixel electrode and the common electrode in a parallel manner with respect to the surface of the substrate, and the director of the liquid crystal molecule is rotated within the horizontal plane so as to perform the LCD display. FIG. 7 is a plan view for indicating the structure of one pixel employed in the liquid crystal display device as described in the above-mentioned official publication document. FIG. 8 is a sectional view for showing this liquid crystal display device, taken along a line E to E of FIG. 7. FIG. 9 is a sectional view for indicating this liquid crystal display device, taken along a line F to F of FIG. 7.
Referring to FIG. 7 to FIG. 9, the structure of the conventional liquid crystal display device will be described.
In the conventional liquid crystal display device, a plurality of scanning lines 3 and a plurality of signal lines 4 are arranged in the matrix form on the transparent insulating substrate 1. Furthermore, the common electrode line 11 is formed in parallel to the scanning lines 3. The thin-film transistor (TFT) 6 is formed, and the pixel electrode 10 electrically connected to the source electrode of the thin-film transistor 6 is formed at the intersection portion of the scanning line 3 and the signal line 4.
As indicated in FIG. 7, the stripe-shaped drawing electrodes are branched from the pixel electrode 10 and the common electrode line 11 and are extended along the direction of the signal line 4. The drawing electrodes connected to the respective electrodes 10 and 11 are staggered in a parallel manner. When the voltage is applied to these drawing electrodes, such an electric field 100 is produced which mainly has the electric field component in parallel to the scanning line 3, and also in parallel to the substrate surface.
Next, the above-described thin-film transistor 6 will be described more in detail with reference to FIG. 9. This thin-film transistor 6 has such a structure, generally called as a "reverse stagger structure" that the channel layer 5, the source electrode 10, and the drain electrode 4 are located above the gate electrode 3.
As indicated in FIG. 9, the gate electrode 3 electrically connected to the scanning line 3 is formed on the transparent insulating substrate 1. The gate insulating film 16 is formed on the entire surface of this gate electrode 3 so as to cover this gate electrode 3.
Then, the amorphous silicon layer 5 is formed on the gate insulating film 16 above the gate electrode 3, and this amorphous silicon layer 5 constitutes the channel layer. The drain electrode 4 is connected to one side of the amorphous silicon layer 5. The drain electrode 4 is electrically connected to the signal line 4. The source electrode 4 is connected to another side of this amorphous silicon layer 5, and the source electrode 10 is further connected to the pixel electrode 10.
It should be noted that the n.sup.+ type amorphous silicon layer 15 to which the n type impurity is doped in high concentration is provided among the drain electrode 4, the source electrode 10, and the amorphous silicon layer 5. The reason why this n.sup.+ type amorphous silicon layer 15 is provided is to establish to ohmic contact among the amorphous silicon layer 5, the drain electrode, and the source electrode. Furthermore, the passivation layer 13 is provided in such a manner that this passivation layer 13 entirely covers all of these components. The TFT-sided liquid crystal orientation layer 17 used to orientate the liquid crystal molecules along the direction suitable for the liquid crystal operation mode is provided on the passivation film 13.
The active element substrate 19 is constituted by the structural elements defined from the above-explained transparent insulating substrate 1 up to the TFT-sided liquid crystal orientation layer 17.
In addition, the counter substrate 20 equal to the color filter (CF) is provided via the liquid crystal layer 14 opposite to this active element substrate 19. As this counter substrate 20, the black matrix layer 7, the color layer 8, and the CF-sided liquid crystal orientation layer 12 are successively stacked on the transparent insulating substrate 2. This black matrix layer 7 is provided so as to hide the thin-film transistor 6, the scanning line 3, the signal line 4, and the like with respect to the external field of this thin-film transistor 6. The counter substrate 20 on the side of the CF-sided liquid crystal orientation layer 12 is faced to the liquid crystal layer.
The above-explained active element substrate 19, liquid crystal layer 14, and counter substrate 20 constitute the active matrix liquid crystal display device.
In this counter substrate 20, when the thickness of the black matrix layer 7 becomes thick, a difference between the thicknesses of the portions within the counter substrate 20, in which the black matrix layer 7 is present and is not present, is increased. The dimensions of the concaves/convexes formed on the substrate of the counter substrate 20 are increased. As a result, since the thickness of the liquid crystal layer 14 sandwiched between the active element substrate 19 and the counter substrate 20 is fluctuated within the panel surface, this thickness fluctuation may cause display fluctuations. To avoid such a difficulty, this black matrix layer 7 is made of a thinner metal in order that the thickness of the black matrix layer 7 can be made thinner.
Referring to FIG. 8, a description will be made of a structure of such a portion that the scanning line 3 is located in parallel to the common electrode line 11. As indicated in this drawing, on the side of the active element substrate 19, both the scanning line 3 and the common electrode line 11 are located in a parallel manner on the transparent insulating substrate 11, on which the gate insulating film 16, the passivation film 13, and the TFT-sided liquid crystal orientation layer 17 are stacked. Also, on the side of the counter substrate 20, there is provided the same structure as that shown in FIG. 9.
On the other hand, different from the conventional TN mode of liquid crystal display device, in the conventional IPS mode of liquid crystal display device, the common electrode 11 is formed on the active element substrate 19, but is not provided on the counter substrate 20. As a result, the metal which constitutes the black matrix layer 7 is set to the floating condition. In this case, the below-mentioned problem will occur.
In the case that the black matrix layer 7 is made of a metal, this black matrix layer 7 owns a certain potential, because this metal black matrix layer 7 is influenced by the potential on the side of the active element substrate 19 located just above the black matrix layer 7. Where there is a difference between the potential owned by the black matrix layer 7 and the potential at the display pixel portion, since the electric field is produced between the black matrix layer and the display pixel portion, the electric field of the display pixel portion would be disturbed.
This problem will now be explained more in detail with reference to FIG. 7 to FIG. 9.
As represented in FIG. 7, the patterns on the side of the active element substrate 19 which is located opposite to the black matrix layer 7 on the side of the counter substrate 20 are subdivided into the scanning line 3, the common electrode line 11, and the signal line 4.
First, as represented in FIG. 8, the black matrix layer 7 on the side of the counter substrate 20 which is located opposite to the scanning line 3 and the common electrode line 11 is capacitive-coupled to both the scanning line 3 and the common electrode line 11 via the color layer 8, the liquid crystal orientation layer 12, the liquid crystal layer 14, the liquid crystal orientation film 17, the passivation film 13, and the gate insulating film 16. On the other hand, as shown in FIG. 9, similar to both the scanning line 3 and the common electrode line 11, the black matrix layer 7 located opposite to the signal line 4 is capacitive-coupled to the signal line 4 via the color layer 8, the liquid crystal orientation film 12, the liquid crystal layer 14, the liquid crystal orientation film 17, and the insulating films 13 and also 16.
Eventually, the potential at the floating black matrix layer 7 corresponding to the electric conductor may be mainly determined based on the respective potentials at the scanning line 3, the common electrode line 11, and the signal line 4, and further the coupling capacitances among the scanning line 3/common electrode line 11/signal line 4, and this black matrix layer 7. This potential of the floating black matrix layer 7 is expressed by the below-mentioned formula (1): EQU V.sub.BM =(C.sub.BM-G /C.sub.tot).times.V.sub.Goff +(C.sub.BM-COM /C.sub.tot) .times.V.sub.COM +(C.sub.BM-D /C.sub.tot).times.VD (1),
where the following symbols are defined:
C.sub.BM-G : a capacitance value between the BM (black matrix) layer 7 and the scanning line appearing on the BM layer 7. PA1 C.sub.tot : a total capacitance value of capacitance values among the scanning line appearing on the BM layer, the common electrode line, and the BM layer. PA1 V.sub.Goff : a potential at the scanning line (TFT transistor is turned OFF). PA1 C.sub.BM-COM : a capacitance value between the common electrode line appearing on the BM layer and the BM layer. PA1 V.sub.COM : a potential at the common electrode. PA1 C.sub.BM-D : a capacitance value between the BM layer and the signal line appearing on the BM layer. PA1 V.sub.D : a potential at the signal line. PA1 (A) a first substrate including a plurality of scanning lines and a plurality of signal lines arranged in a matrix form; a common signal line extended in parallel to one of the scanning lines and the signal lines, for applying a reference potential thereto; a pixel electrode; and a thin-film transistor having a source electrode connected to the pixel electrode, a drain electrode connected to the signal line, and a gate electrode connected to the scanning line, the thin-film transistor being formed in an intersection portion between the scanning line and the signal line; PA1 (B) a second substrate including a black matrix layer and positioned opposite to the first substrate with sandwiching a liquid crystal layer between the first substrate and the second substrate; and PA1 (C) an insulating layer sandwiched between the pixel electrode of the first substrate and the scanning line; wherein: PA1 the gate electrode formed on a transparent insulating substrate; PA1 a gate insulating film for covering the gate electrode; PA1 a channel layer formed on the gate insulating film over the gate electrode; PA1 the gate electrode and the drain electrode, which are formed in both edge portions of the channel layer; and PA1 an insulating layer for covering the channel layer, the source electrode, and the drain electrode. PA1 (A) a first substrate including a plurality of scanning lines and a plurality of signal lines arranged in a matrix form; a common signal line extended in parallel to one of the scanning lines and the signal lines, for applying a reference potential thereto; a pixel electrode; and a thin-film transistor having a source electrode connected to the pixel electrode, a drain electrode connected to the signal line, and a gate electrode connected to the scanning line, the thin-film transistor being formed in an intersection portion between the scanning line and the signal line; PA1 (B) a second substrate including a black matrix layer and positioned opposite to the first substrate with sandwiching a liquid crystal layer between the first substrate and the second substrate; and PA1 (C) an insulating layer sandwiched between the pixel electrode of the first substrate and the scanning line; wherein: PA1 (A) a first substrate including a plurality of scanning lines and a plurality of signal lines arranged in a matrix form; a common signal line extended in parallel to one of the scanning lines and the signal lines, for applying a reference potential thereto; a pixel electrode; and a thin-film transistor having a source electrode connected to the pixel electrode, a drain electrode connected to the signal line, and a gate electrode connected to the scanning line, the thin-film transistor being formed in an intersection portion between the scanning line and the signal line; PA1 (B) a second substrate including a black matrix layer and positioned opposite to the first substrate with sandwiching a liquid crystal layer between the first substrate and the second substrate; and PA1 (C) an insulating layer sandwiched between the pixel electrode of the first substrate and the scanning line; wherein:
It should be noted that since the capacitance coupling between the TFT portion and the black matrix layer 7 is very small, as compared with the above-explained other capacitive-coupling, the first-mentioned capacitive coupling is omitted.
On the other hand, when the active matrix LCD device is driven in the polarity inversion, it is conceivable that an average potential of the potentials at the signal line 4 is equal to the potential at the common electrode line 11. As a consequence, it is also conceivable that an average potential at the display pixel portion is substantially equal to the potential at the common electrode line 11. As a consequence, there is no risk that the potential at the black matrix layer 7 never greatly disturbs the electric field of the display pixel portion. However, as apparent from the below-mentioned formula (2), since the potential at the black matrix layer 7 is further influenced by the potential at the scanning line 3, this potential of the black matrix layer 7 becomes such a value deviated from the potential at the common electrode line 11 only by: EQU (C.sub.BM-G /C.sub.tot).times.(V.sub.GOff -V.sub.COM) (2).
As a consequence, in the conventional active matrix LCD device having the above-explained structure, since the potential at the black matrix layer 7 may disturb the electric field of the display pixel portion, there is the display fluctuation problem.
Also, in the wide view angle LCD device, the birefringent characteristic (double refraction characteristic) of the liquid crystal 14 must be precisely controlled by the electric field appearing in parallel to the plane of the substrate 19. The electric field on the color filter contains the vertical component with respect to the substrates 19 and 20. Since the liquid crystal molecules are rotated along the direction perpendicular to the substrates 19 and 20, the birefringent characteristic of the liquid crystal 14 is largely changed, so that the degree of the display fluctuation becomes very large, as compared with that of the TN mode of the LCD device.